During the manufacture of solar cells, poor passivation may result in a presence of localized wafer regions with inferior properties deteriorating cell efficiency. Such typical defects in wafers with passivated emitters are manifested in regions with high emitter saturation current, J0, or low open circuit voltage, Voc.
J0 is a parameter that describes losses caused by the recombination of excess carriers (electrons with holes) in the emitter region of a wafer, including surface or interface recombination, and is important for solar cell operation. Passivation is the process designed to reduce such loses. Engineering of effective passivation involves two elements: 1) reduction of the density of interface traps that act as recombination centers; and 2) creation of the electric field barrier that repels one type of carrier from the emitter (for example electrons) preventing the recombination process that requires both type of carriers (electrons and holes).
For very high efficiency thin silicon cells made with high bulk lifetime silicon wafers, the recombination loses of carriers in the bulk silicon (base region) become less important than losses due to recombination in the emitter. For such cells, development of very efficient emitter passivation becomes of increasing importance. The process of passivation is a difficult one. It may be done by deposition of stacked dielectric film structures on the emitter (with top dielectric layer also serving as antireflection coating, ARC). In some high efficiency cells the passivation is done employing amorphous Si layers rather than dielectrics, and the corresponding heterojunction barriers with silicon reduce the recombination. The effectiveness of passivation can be enhanced by hydrogenation and proper post-deposition rapid annealing.
By eliminating the passivation defects, the efficiency of silicon solar cells can be improved, especially for high efficiency cells. This can have a positive impact on competitiveness of silicon photovoltaics in a clean energy market.
An important element in such an effort is the ability to produce whole wafer maps of J0 and Voc (or the implied Voc) that are suitable for in-line processing monitoring in silicon PV fabrication.